The present invention relates to a code signal detector which is included in a character broadcast receiver for receiving a broadcast with characters superimposed and which is used to detect and correct a 1-bit error included in a framing code signal among characters transmitted.
FIG. 1 schematically illustrates the waveforms of character broadcast signals. The character signals are superimposed over a television video signal during one or more horizontal scan line periods included in a vertical blanking line. The resultant composite signals are transmitted. Referring to FIG. 1, a section A comprises a bit synchronization signal for obtaining a synchronous clock signal which is used for extracting the succeeding information. The bit synchronization signal is called a clock run-in (CR) signal.
A section B comprises a signal called a framing code (FC) signal which is used for synchronization of data packets appearing at a time in and after a section C. At present, the code assigned to the framing code in the character broadcast of Japan is "11100101" as illustrated in FIG. 1.
FIG. 2 shows a conventional code detector for detecting the FC signal. This circuit configuration is disclosed in the reference, "A proposal of a new scheme (packet scheme) for the character broadcast", 4-1-1-WG-9 which has been submitted from the Japan Broadcasting Corporation to the character broadcast working party in the Radio Technical Council of the Ministry of Postal Services in Japan. The FC signal is so detected that even an FC signal having a 1-bit error may be detected to increase the detection reliability.
Referring to FIG. 2, reference numeral 4 denotes a shift register for converting the FC signal supplied serially on the time sequence into a signal having a parallel form. Reference numerals 5, 6 and 7 respectively denote a NOT gate, a NAND gate and a negative-logic OR gate. The FC signal transmitted serially on the time sequence is converted into a signal composed of 8 parallel bits by the shift register 4. Bits corresponding to logical "0" states in the FC signal are respectively inverted by NOT gates 5. If a correct FC signal is sent out from the shift register 4, it passes through a NAND gate 6 depicted at the top of FIG. 2. As a result, the negative-logic OR gate 7 sends out the FC detection signal. If an FC signal including a 1-bit error is sent out from the shift register 4, one of 8 subcircuits each of which comprises a NAND gate 6 and a NOT gate 5 sends out a signal to be converted into the FC detection signal. In these subcircuits, a NOT gate 5 is connected to one input of each subcircuit. As the location of the subcircuit descends, the position of the input of the NAND gate whereto the NOT gate is connected is shifted down. This results in 1-bit error correction.
However, the circuit of FIG. 2 has a drawback that the circuit for correcting a 1-bit error requires complicated wiring, often causing a failure or false operation.
Further, in the detector illustrated in FIG. 2, the output terminals of the shift register 4 whereto the NOT gates 5 are connected are predetermined according to the pattern of the code signal. Therefore, the detector cannot respond to a code signal transmitted from another broadcasting station having a pattern which is different from the above described predetermined pattern.